Substrate Design Services to Create Flexible, Low-Cost Packaging Solutions

QP Technologies expands capabilities related to interposer designs for flip-chip and large-cavity packaging.

FREMONT, CA: QP Technologies, a leading provider of innovative microelectronic packaging and assembly solutions, announces expanded capabilities connected to interposer designs for flip-chip and large-cavity packaging extensions the firm's substrate design services advertised last year.

Customers that come to the firm with a flip-chip die often can't, or don't want to, expend dollars on creating a redistribution layer or a custom package. They require a solution that will enable them to package the flip-chip quickly and cost-effectively using existing technology. The team can help them choose the right package and substrate materials or adapt what they have and need to continue using to remediate their packaging challenges.

QP Technologies can develop an interposer-powered prototype that allows the customer to avoid the time and expense of recreating the test hardware. This enables the reuse of legacy platforms without generating a new package solution, which the firm also creates for those who want them.

QP Technologies offers flexible interposer design alternatives for adapting existing packages to redistribute flip-chip connections to wire bonds or shorten bond wire lengths. Modern wire bonders, particularly those with the tight pitch need for smaller die, have practical distance limitations for wire spool-out, needing creative wiring techniques to accommodate more extensive packages, such as ceramic or plastic pin grid arrays (PGAs). Quik-Pak references the customer's die bond pad layout to design an interposer solution that allows flip-chip attach in a package for wire bond or reduces wire lengths letting interconnections, leveraging organic F4R or silicon substrates, depending on customer demands.

Applications that can advantage of this approach include memory devices and IP cores. Memories use expensive testbeds that take a long time to characterize and develop, so the device makers need to retain the template's PGA format. In the IP space, retesting is required with each new node, so maintaining the same package is highly beneficial, particularly when validating the IP for multiple nodes or foundries.